CMP Defect Monitoring in HKMG Loop on Monitor Wafers
Conference: ICPT 2012 - International Conference on Planarization / CMP Technology
10/15/2012 - 10/17/2012 at Grenoble, France
Proceedings: ICPT 2012
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Peng, Ren; Hsu, Chun Wei; Hsieh, Duckblood; Lin, Welch; Huang, Climbing; Wu, JY (United Microelectronics Corporation, Tainan Science, Tainan County 741, Taiwan, R.O.C.)
Palamadai, Chandar; Sapre, Prasanna; Chang, Timothy; Wang, Tony; Huang, Eros; Cheng, Harvey; Hu, Debbie (KLA-Tencor Corporation, One Technology Drive, Milpitas, CA 95035, USA)
High-K Metal Gate (HKMG) is one of the most significant steps in CMOS manufacturing for 28nm node process and beyond. For Metal Gate step to be accurately controlled the Chemical-mechanical planarization (CMP) method is required for surface planarization. CMP process creates a lot of defects on the wafer surface. Minimization of defects in CMP process is of inherent interest as these defects can lead to manufacturing yield excursions. Scratches, particles, slurry residues are some of the key defects of this process. Scratches are of special interest as they are often killer defects, which reduce the overall yield by a large extent. In this article, detection and identification of particles on oxide CMP surfaces and scratches on Al CMP surface will be presented. The enhancement of scratch detection with the use of high resolution haze images will be also be shown. In addition, an optimization method of different phases of polishing time during CMP is clearly brought out. The methodology described in this paper has already been proven to be quite effective in monitoring the CMP process. Keywords: CMP, Defect Monitoring, Sensitivity, Polishing Times, SP2, SURFmonitor.