Process Optimization of Grinding and CMP for Thinning of Si
Conference: ICPT 2012 - International Conference on Planarization / CMP Technology
10/15/2012 - 10/17/2012 at Grenoble, France
Proceedings: ICPT 2012
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Feeney, Paul; Shumway, Lynn (Axus Technology, 7001 W. Erie St, Chandler AZ, USA)
The use of thinning processes for Si wafers prior to packaging continues to grow. With the advent of 3DIC's, sensor/MEMS, and other advanced applications, the need for improvement in the quality of the resulting surface has gone up significantly. Final process steps often include polish processes of 10 minutes or more after the grinding steps in order to meet the specifications for the roughness and defectivity for subsequent processing. Since the amount of Si removal du ring polishing can be greater than 10 microns, any non-uniformity of the polish can increase the Total Thickness Variation (TTV) of the wafer. Generally TTV values need to be less than 3 microns, so variation from the polishing needs to be controlled. Innovation in the abrasives and binding resins of grinding wheels has created an opportunity to produce ground wafers with improved surface finish. This in turn reduces the amount of Si removal during CMP.