Influence of different anneal processes on copper surfaces pre - and post - CMP

Abstract:
The chip integration design has changed from long, wired, two-dimensional packaging to short, vertical, three-dimensional stacking. New challenges have to be mastered with the introduction of Through Silicon Vias (TSVs) as a key element in 3D Integration. Though-silicon via (TSV) technology has received the most attention because this technique offers system design flexibility, low cost, and integration of heterogeneous chips. [1] This includes the development and validation of concepts for 1) TSV formation, 2) metal layer build-up, 3) various types of assembly and packaging concepts and methods, as well as 4) process characterization. Goal was to develop a flexible and modular technological concept which allows the execution and characterization of the above mentioned processes by using a test- and characterization wafer (ASSID-TC). This paper will focus on the influence of the anneal temperature on the copper surface around the filled TSV holes by using the ATEC for process optimization. After TSV fill by ECD the copper surface appears rough and shows non-uniformities around the TSV holes (“dip”- shape or “groove”). These irregularities were measured after ECD up to 2micrometer depth. Without a temperature treatment prior CMP the “dip” gets transferred down to the barrier and reduced in depth also to the isolation layer. The dimension of this “groove” after CMP is similar to erosion and dishing. It has been be demonstrated that a temperature treatment is advised as well to avoid not just copper protrusion but rather also the “dip” influence to the planarization if these planarization parameters are important for the integration (depending from product). Keywords: Through Silicon Via (TSV), Anneal, CMP, Test Chip, ECD, Copper, Erosion, Dishing, Protrusion