Advances in CMP for TSV Reveal

Conference: ICPT 2012 - International Conference on Planarization / CMP Technology
10/15/2012 - 10/17/2012 at Grenoble, France

Proceedings: ICPT 2012

Pages: 4Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Rhoades, Robert L. (Entrepix, 2315 W. Fairmont Drive, Tempe, AZ 85282, USA)
Malta, Dean (RTI International, 3040 Cornwallis Road, Research Triangle Park, NC 27709, USA)

Microelectronic devices using through silicon vias (TSV’s) are now available in the market for some advanced applications and many more are being developed. The design goals usually include reducing parasitic losses and shrinking final form factors. The process sequence for a TSV module generally requires a combination of deep via etch, liner deposition, barrier deposition, via fill, damascene CMP (Cu or other conductor), temporary carrier mounting, thinning, stress relief and via reveal steps. The last step, via reveal, is the focus of this presentation. After forming the TSV’s and finishing other process steps from the front or device side of the wafer, a typical process sequence then proceeds to mounting the device side to a carrier substrate and using backgrind to remove a substantial portion of the original device substrate. The Si remaining over the vias (from a few microns to several 10’s of microns) is driven by the original TSV etch depth and the target amount to be removed in the reveal step which are two of the design parameters. In some integrations, the via reveal step consists of a single step CMP process to remove the rest of the Si, as well as the liner and barrier layers in the original “bottom” of the via, exposing the conductive core at the center of the TSV. In this case, the via reveal step is performed entirely with CMP and must be developed to achieve the following: remove Si at a high rate to avoid overly long polish times, remove the oxide liner covering the bottom of the via, remove the barrier metal, planarize the Cu with the surrounding surface and provide controlled topography (low dishing), low roughness and low defectivity (no scratching). For several years, the common approach to this set of goals has been a multi-step polishing sequence with at least 2 and sometimes 3 different slurries on different pads on a multi-platen polisher. Data will show that all of these goals can be achieved using a single slurry on a single polishing pad. Numerous other TSV process sequences have been developed, some of which involve a selective Si etch to remove the bulk Si until the vias protrude. In these integrations, the tops of the TSV’s are not covered in Si but are still encased in the original barrier and liner layers. Their height above the surface is typically from one to a few microns. The challenge of CMP in these situations is to get through the liner layers and planarize the topography quickly while removing as little as possible from the field areas between vias. Promising new slurries have been developed that enable this process result in a very reasonable polish time. As often happens with new integrations, changes in materials or upstream process targets can have a major impact on the CMP step, some of which will also be discussed.