Study on Polishing Properties for Phase Change Memory

Conference: ICPT 2012 - International Conference on Planarization / CMP Technology
10/15/2012 - 10/17/2012 at Grenoble, France

Proceedings: ICPT 2012

Pages: 4Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Bae, Jinwoo; Lee, Wonjun; Park, Seungho; Lee, Jae-Dong; Hwang, Inseak; Nam, Seok-Woo (Process Development 1`Project, Semiconductor R&D Center, Hwasung Campus, Samsung Electronics Co., Ltd., Banwol-Dong, Hwasung-City, Kyunggi-Do, 445-701, Korea)

In this paper, chemical mechanical planarization (CMP) process for GST material was studied to improve the electrical performances of sub-20nm PRAM device. The surface of GST material was dependent on the final treatment methods such as gas-phase etching and CMP. Although the GST CMP process exhibited better electrical performances for PRAM, it was very difficult to get the desirable GST CMP solutions due to the complicated GST material characteristics such as density, composition, doped component, and so on. Especially, the removal rate (RR) of GST was low for a GST film of sub-20nm PRAM device which was adopted a damascene structure. To overcome long process time for GST CMP, the combined approaches with gas-phase bulk GST etching and final GST CMP technology were suggested. The present work developed the gas-phase etching method having limited surface damage on GST film and the GST CMP process having sophisticated GST removal control with the designed GST CMP slurry. The proposed solution showed an enhanced device fluctuation performance and a 42% reduction in GST set resistivity(Rset). Keywords : PRAM, GST, CMP, Te, Residue, Density