On the Influence of Layout Parasitics on the Design of a CMOS LNA at 5.5 GHz
Conference: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 13. ITG/GMM-Fachtagung
03/04/2013 - 03/06/2013 at Aachen, Deutschland
Proceedings: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Dang, J.; Milady, S.; Hinz, M.; Meinerzhagen, B. (BST, TU Braunschweig, Postbox 3329,38023 Braunschweig, Germany)
In many analog designs devices requiring a large area like on chip spiral inductors and transmission lines are often connected to other devices requiring only a small area like MOS-transistors. This implies that rather long metal line connections between these devices are often unavoidable. These long connections introduce additional parasitic elements and for higher frequencies even additional inductances need to be considered and require the application of electromagnetic simulation for their accurate modeling. These layout related extra parasitic elements often seriously degrade the performance of the initial designs and make a redesign necessary. For a successive redesign it is very crucial to have a deeper understanding about the underlying reason of the performance degradation which is normally not provided by electromagnetic simulation but ideally requires a simple analytic model. This is demonstrated in this paper based on the design, layout, pre- and post-layout modeling and experimental characterization of a low noise amplifier at 5.5 GHz.