Statistical analysis of SRAM cells for high end processors in newest CMOS process technology
Conference: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 13. ITG/GMM-Fachtagung
03/04/2013 - 03/06/2013 at Aachen, Deutschland
Proceedings: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Payer, Stefan; Kugel, Michael; Pille, Jürgen; Wendel, Dieter (IBM Deutschland Research & Development GmbH, Böblingen, Deutschland)
Each new technology enables the usage of more and more transistors in every new generation of processors, the increasing amount of caches and their size are one consumer of transistors. While the amount of cells is increasing, each new technology is getting closer to physical limits. Therefore process variability of the SRAM cell transistors in manufacturing of a processor is getting more and more influence on the yield. This creates the need for statistical analysis and simulations of the SRAM cells across process variation in read stability, write ability and read performance to ensure robust caches and memories, which will work up to process variations on certain probabilities. This methods and analysis are used in product development cycle to enable high end processors for IBM Power Systems and IBM System z.