Short Term NBTI Degradation in Switched-Capacitor Circuits
Conference: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 13. ITG/GMM-Fachtagung
03/04/2013 - 03/06/2013 at Aachen, Deutschland
Proceedings: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Heiß, Leonhard; Yilmaz, Cenk; Werner, Christoph; Schmitt-Landsiedel, Doris (Lehrstuhl für Technische Elektronik, Technische Universität München, Germany)
Due to non constant field scaling and introduction of nitrided gate oxides, negative bias temperature instability (NBTI) has become a significant reliability issue in modern CMOS technologies. The main impact of NBTI stress is a change of the threshold voltage of pMOS transistors which can partly recover during subsequent relaxation. State of the art reliability research assumes that this NBTI induced Vth-shift builds up only slowly compared to common operating frequencies of CMOS circuits and thus causes circuit failure merely after several years of operation. Besides this well-known long term degradation, the application of short stress pulses causes threshold voltage shifts in the mV regime and subsequent relaxation as well . Although such transient variations of Vth due to short term NBTI effects can cause failures in analog circuits , , the effect got hardly investigated in former research on circuit reliability. In this paper we will discuss a new approach to model short term device degradation. Using our model, we will give novel insights into the impacts of short term NBTI on a switched-capacitor comparator and a successive approximation analog-to-digital converter in a 65 nm technology.