Design of a 12-bit cyclic RSD ADC Sensor Interface IC using the Intelligent Analog IP Library
Conference: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 13. ITG/GMM-Fachtagung
03/04/2013 - 03/06/2013 at Aachen, Deutschland
Proceedings: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Reich, Torsten; Eichler, Uwe; Rooch, Karl-Heinz; Buhl, René (Fraunhofer Institute for Integrated Circuits, Design Automation Division, Dresden, Germany)
Within this paper we present an Intelligent Analog IP design flow and its successful application on an industrial-level mixed-signal ASIC design. This novel design flow is based on a library of flexible (configurable), robust (Design for reliability awareness) and technology-independent Analog IPs, available from primitive device level up to complex circuit blocks. Its application leads to a significant increase in efficiency of the overall design process due to reduced design and layout cost, speed-up or even avoidance of redesign cycles and very fast technology porting. For the design of a multi-physical SMART sensor interface with a low-power 12-bit RSD ADC we already saved 43 % of layout time using the Intelligent Analog IP design flow. In addition, system-level and schematic design as well as post-layout verification was more efficient compared to conventional design flows.