Sequential Hierarchical Model-order Reduction for Robust Design of Parameter-varying Systems
Conference: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 13. ITG/GMM-Fachtagung
03/04/2013 - 03/06/2013 at Aachen, Deutschland
Proceedings: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden
Pages: 5Language: englishTyp: PDF
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Authors:
Hauser, Matthias; Lang, Patrick (Fraunhofer Institute for Industrial Mathematics, Fraunhofer-Platz 1, 67663 Kaiserslautern, Germany)
Abstract:
In this paper we introduce a method for the hierarchical model order reduction of parameter-varying analog circuits. A new concept is presented that reduces the circuit’s blocks to build a reduced overall model that does not violate a predefined error bound. An additional acceleration of the reduction process is achieved by introducing a sequential workflow of the reduction algorithm. Finally for illustration, we apply the overall procedure to the operational amplifier OpAmp 741 and compare it to the standard methods.