Histogram on the Track
Conference: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden - Vorträge der 13. ITG/GMM-Fachtagung
03/04/2013 - 03/06/2013 at Aachen, Deutschland
Proceedings: ANALOG 2013 - Entwicklung von Analogschaltungen mit CAE-Methoden
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Rantisi, Mohammed (LZS, University Erlangen-Nürnberg, Erlangen, Germany)
Sattler, Sebastian (University Erlangen-Nürnberg, Erlangen, Germany)
DNL testing requires a lot of time. Testing time is very expensive but it is necessary at most. Several methods are available to implementing DNL testing. The fastest and most efficient methodology is the Histogram-Test. The higher the resolution is the longer the testing time, independent of the used method. But, Histogram Test is not correct as it was thought to reveal today. This document illustrates the Histogram Test and shows by measurement results that the histogram for DNL testing with 80 hits per code could be improved. It shows that the testing time of a 16-bit ADC of 1 MSPS () can be reduced from 5s to a minimum of 77ms maintaining still the quality of testing.