PD-SOI MOSFET Performance Optimization for High Temperatures up to 400 °C Using Reverse Body Biasing

Abstract:
SOI (Silicon-on-Insulator) MOSFET device performance, i.e. intrinsic gain and bandwidth, in a wide temperature range up to 400 °C has so far been strongly affected by device leakage currents. Also the moderate inversion region as a desired point of operation has been unusable as leakage currents dominate drain currents at high temperatures. In this paper we present a reverse body-biasing (RBB) approach to reduce leakage currents and simultaneously improve the transistor’s performance up to 400 °C. Thereby operation in the lower moderate inversion region of the SOI transistor device is feasible. The method presented here allows beneficial FD (fully depleted) device characteristics in a 1.0 µm PD (partially depleted) SOI CMOS process. Split-Source NSOI and NHGATE devices with an H-shaped gate have been investigated. Results report a leakage current reduction of 97 % and a 670 % improvement of the gm/Id factor in the moderate inversion region the NHGATE device by applying the presented technique.