Direct integration of carbon nanotubes on CMOS with high-temperature tungsten metallization
Conference: Mikro-Nano-Integration - 4. GMM-Workshop
11/12/2012 - 11/13/2012 at Berlin, Deutschland
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Jupe, A.; Hoeren, A.; Goehlich, A.; Vogt, H. (Fraunhofer Institute for Microelectronic Circuits and Systems IMS, 47057 Duisburg, Germany)
Meißner, F.; Endler, I. (Fraunhofer Institute for Ceramic Technologies IKTS, 01277 Dresden, Germany)
Currently carbon nanotubes (CNTs) can be synthesized by a CVD process at deposition temperatures of about 700deg C. The direct deposition of CNTs on standard CMOS substrates with aluminium metallization is impossible due to the maximum tolerable temperature budget of approximately 450deg C. The influence of the additional deposition temperature for CNT synthesis causes intolerable parameter shifts of the electrical devices as well as damages of the metallization. In this report we present experimental runs obtained with different CMOS technologies and characterize the influence of an annealing step (30 min up to 700deg C) on the threshold voltage of n-channel und p-channel MOSFETs as well as the effect on the metallization. After annealing at 700deg C / 30 min the combination of a conventional 0.8 µm - bulk substrate technology with tungsten metallization shows parameter shifts of threshold voltage in an acceptable range, so this CMOS technology is particularly suitable for direct deposition of CNTs on CMOS. Results of CNT synthesis with mixed catalysts are presented.