A proposal of embedded SoC power supply compatible with a digital block design flow
Conference: CIPS 2014 - 8th International Conference on Integrated Power Electronics Systems
02/25/2014 - 02/27/2014 at Nuremberg, Germany
Proceedings: ETG-Fb. 141: CIPS 2014
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Souvignet, Thomas; Trochut, Severin; Hasbani, Frederic (STMicroelectronics, Crolles, France)
Allard, Bruno (Ampere lab INSA Lyon, Villeurbanne, France)
The power supply embedded in a SoC in advanced CMOS comprises a power domain per block. The introduction of a local dedicated DC-DC converter modifies significantly the resource usage and the design flow within the valuable digital block. A suitable architecture of Switched Capacitors (SC) DC-DC converter is considered. This architecture must lead to an effective area not larger than the one of the digital block including the power switch ring. The DC-DC converter should provide the necessary voltage ratios what means the usage of a cell-based architecture. The paper details the specifications and operation of the proposed architecture of SC DC-DC converter using MIM capacitors. The capacitors are stacked above the digital area and the power switches are reused by the converter. A special care is provided in the usage of metal resources, the MIM capacitors distribution and interconnections, the clock distribution and the power MOSFET place and route. A proposed SC DC-DC converter of 0.54 mm2 is implemented in a 28nm FDSOI process from STMicroelectronics. The input voltage is 1.8V. The voltage regulator exhibits 4 conversion ratios: 3:1, 2:1, 3:2 and 4:3. A current density of more than 0.4 A/mm2 is achieved with 74 % peak efficiency but sufficient flatness. MIM capacitor usage offers no area overhead. Simulation results are discussed. A test chip is under fabrication for experimental results to be presented at time of conference.