Novel Layout and Packaging for Lateral, Low-Resistance GaN-on-Si Power Transistors
Conference: CIPS 2014 - 8th International Conference on Integrated Power Electronics Systems
02/25/2014 - 02/27/2014 at Nuremberg, Germany
Proceedings: ETG-Fb. 141: CIPS 2014
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Reiner, R.; Waltereit, P.; Benkhelifa, F.; Walcher, H.; Quay, R.; Schlechtweg, M.; Ambacher, O. (Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany)
This work introduces an innovative layout structure for lateral, low-resistance GaN-based power transistors, designed for use in TO220 packages. Design aspects for large gate width transistor structures of up to 359 mm and the inhomogeneous power distribution on active area and metallization of such structures are discussed. The new layout is realized using an AlGaN/GaN-on-Si technology. The devices are packaged and characterized. Results are directly compared to those obtained from a conventional comb structure. The fabricated device achieves drain currents of up to 90 A and on-state resistances as low as 50 mO.