Integrated gate driver circuits with an ultra-compact design and high level of galvanic isolation for power transistors

Conference: CIPS 2014 - 8th International Conference on Integrated Power Electronics Systems
02/25/2014 - 02/27/2014 at Nuremberg, Germany

Proceedings: ETG-Fb. 141: CIPS 2014

Pages: 6Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Authors:
To, N.-D.; Rouger, N.; Crebier, J.-C.; Lembeye, Y. (Univ. Grenoble Alpes, CNRS, G2Elab, ENSE3 bat D, 961, rue Houille Blanche, BP 46, 38402 St Martin d'Heres Cedex, France)
Arnould, J.-D.; Corrao, N. (Univ. Grenoble Alpes, CNRS, IMEP-LAHC, Campus Minatec, 3 Parvis Louis Neel, CS 50257, 38016, Grenoble, France)

Abstract:
A proposed approach for the design and implementation of an integrated gate driver for high switching frequency is shown in this paper. This gate driver represents a compact solution integrating the required functions within a single CMOS chip. A coreless transformer in a 0.35 µm H35B4M3 CMOS technology from AMS is also integrated to ensure the galvanic isolation and gate signal transfer. An analytical model to predict the behavior of the integrated transformer is represented and then compared to the results of electromagnetic simulation and measurements in order to validate the models. A good agreement was observed over a wide range of frequency between these models. Finally, the detailed functionalities and the operating validations of the integrated gate driver will be shown and discussed.