Fan-out Wafer Level Packaging for MEMS and Sensor Applications

Abstract:
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. This technology also offers opportunities for highly miniaturized sensor packages including stress sensitive MEMS components. This paper describes the use of advanced molding techniques as compression molding for single and multi-chip embedding into a reconfigured wafer in combination with either standard thin film technology or large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. One application scenario described here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. For this application the technology proof of concept is demonstrated with a functional two chip package consisting of an acceleration sensor and an ASIC. On top of this package a second wafer level embedded package is assembled containing a pressure sensor and an ASIC. Both WL packages are connected by through mold vias and soldered to a base substrate. The second application described the Fan-out Wafer Level packaging of a CMOS biosensor for integration into a microfluidic diagnostic platform. Here, FOWLP allows an easy integration into microfluidic channel with direct contact of the active sensor area into the microfluidics and sealing on the package fan-out area. By integrating through mold connection e.g. with trough silicon vias (TSV) dies electrical sensor signals can be routed to the backside of the module and hence giving a separation between “wet” microfluidic side and “dry” electrical connection. In summary this paper describes the opportunities of Fan-out Wafer Level Packaging for sensors and sensor systems backed by two successfully demonstrated applications from consumer MEMS and biomedical packaging.