FPGA Implementation of a Data-Aided Single-Carrier Frequency-Domain Equalizer for Format-Flexible Receivers

Abstract:
Format-flexible transceivers belong to the key components of software-defined networking which allows for dynamic reconfiguration to react to changing bandwidth demands. Enabled by the use of fast digital-to-analog (DAC) and analog-to-digital converters (ADC), coherent transmission technology is naturally compatible with this concept. Digital signal processing (DSP), in particular on the receive side, should support the flexibility. Data-aided algorithms have recently been shown to provide good and stable equalization performance regardless of the modulation format while requiring only small overhead for the training sequences. The efficient real-time implementation of such algorithms remains a challenge. In this contribution, we report on an implementation of a data-aided single-carrier frequency-domain equalizer on a field-programmable gate array (FPGA). In a hardware-in-the-loop co-simulation setup we compare the performance of the FPGA implementation and an unconstrained floating point implementation. Polarization-division multiplexed (PDM) 4-quadrature amplitude modulation (4QAM), PDM-16QAM and PDM-64QAM samples from simulation and experiment are processed to study the trade-off between fixed-point complexity and equalizer performance. For moderate fixed-point resolutions low performance penalties compared to the floating-point implementation are observed.