Correcting Delay Faults and Transient Faults in Pipelines

Abstract:
Digital circuits and systems implemented in nano-technologies tend to show a larger variety of fault effects in on-line operation than previous systems. Of special concern have been single- and multiple event upsets (SEUs, MEUs) and single / multiple event transits (SETs, METs), induced by particle radiation, and, more recently, delay faults caused by aging effects. Work in this area has yielded several special architectures that are tailored for the detection and compensation of one class of faults, but rarely at the compensation of theses faults combined at reasonable cost. Furthermore, some well-published architectures work only on implicit assumptions on fault effects, such as the more or less random introduction of delays on specific paths, which is no longer valid in case of aging-introduced delays. Therefore it is necessary to know how such methods can be modified to cover all stage inputs / outputs in a pipelined architecture. Work presented here shows a comparison of designs that may catch and compensate delays and transient faults in pipelined architectures and shows a comparison of shortcomings, limitations and cost / overhead.