Low-Effort On-Board Memoryless Predistortion Techniques for SATCOM
Conference: SCC 2017 - 11th International ITG Conference on Systems, Communications and Coding
02/06/2017 - 02/09/2017 at Hamburg, Germany
Proceedings: ITG-Fb. 268: SCC 2017
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Usman, Ovais Bin; Delamotte, Thomas; Knopp, Andreas (Munich University of the Bundeswehr, Chair of Signal Processing, 85579 Neubiberg, Germany)
The emergence of on-board processors (OBPs) allows the manipulation of signals at the satellite transponder which can lead to efficient implementation of digital predistortion techniques. However, due to limitations like the weight, power and radiation hardening requirements of the hardware in satellites, generally less powerful digital signal processors (DSPs) and field programmable gate arrays (FPGAs) are employed onboard. This paper provides a comparison between the existing memoryless Pth order inverse predistortion technique and an improved low-effort and less complex Kth order memoryless polynomial predistortion technique, both of which can be directly implemented in satellites using OBPs. The latter predistorter uses a modified LMS algorithm to find the optimum predistorter which leads to a lower residual error and bit error ratio (BER) with a faster convergence as compared to traditional LMS algorithms. The simulation results presented show that by implementing digital predistortion on-board we can not only achieve gains in the system BER performance but also in the power efficiency due to the reduced input back-off (IBO) and output back-off (OBO) requirements of the HPA.