Estimation of Trends for Coherent DSP ASIC Power Dissipation for different bitrates and transmission reaches

Abstract:
The ongoing demand for increasing the capacity of optical networks drives the continuous development of optical transceiver technology towards smaller module sizes, power consumption and cost while increasing the available bitrate per module. Coherent Telecom transceivers are more and more shaped into standardized pluggable modules of the compact form-factor pluggable (CFP) module family. Coherent pluggables are expected to reach bitrates above 200 Gb/s over metro and long-haul distances but have to comply with the tolerable module power dissipation at the same time. Thereby, the major obstacle is the large power consumption of the digital signal processing (DSP) required to combat channel impairments. Fortunately, Moore’s law promises the permanent reduction of application-specific integrated circuits (ASIC) power consumption. At the same time, improvements on DSP algorithms and the analog frontend will lead to a reduction of the implementation penalty and allow operation closer to the Shannon limit. Based on this perspective, it is instructive to estimate the evolution of the DSP ASIC power consumption within the next years in order to give a forecast on the availability of coherent pluggable modules for different bitrates, transmission reaches and module sizes. To achieve this goal, we develop a simple model which contains scaling laws of the complexity for the key DSP building blocks with respect to varying reach, bit- and symbol rate. Based on the published power breakdown of a reference transceiver, we extrapolate the power dissipation for different spectral efficiencies. In order to find the relation between power dissipation and achievable reach, we first relate spectral efficiency to the required signal-to-noise ratio (SNR) assuming an end-to-end additive, white Gaussian noise (AWGN) channel and Shannon’s capacity theorem. In a second step, the available SNR at a certain reach is calculated by the Gaussian noise (GN) model. Under the general assumption that the ASIC is designed to operate at optimum spectral efficiency, i.e. the achievable rate is maximized for a given available SNR, we can estimate the required ASIC power dissipation for different bit rates and reaches and establish margins for typical module power classes over the next years.