Accelerated Mixed-Signal Simulations Using Multi-Core Architecture
Conference: FAC 2017 - Frontiers in Analog CAD
07/21/2017 - 07/22/2017 at Frankfurt am Main, Deutschland
Proceedings: Frontiers in Analog CAD (FAC 2017)
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Divanbeigi, S.; Aditya, E.; Olbrich, M. (Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany)
With every technological achievement in electronics, new applications and concepts can be realized in circuits. One such concept is System-on-Chip (SoC) that enables developers to integrate a whole system on one physical chip. This is normally used to combine analog and digital systems. Nevertheless, prototyping such a system is resource intensive. This is caused by detailed requirements of analog components, especially nonlinear characteristics, taking the majority of computation resource. Several methods have been implemented to reduce the load, such as by changing the nonlinear behavior to a piecewise linear model and more abstract language description, e.g. SystemC instead of HDL. On the hardware perspective, runtime reduction through clock frequency scaling already reached saturation point, where any improvement only provides a marginal decrease. This and the prevalence of multi-core processors give rise to importance of parallelizing software to utilize the capabilities provided by the platform. Here we present modifications of PRAISE (Piecewise Rapid Analog Integrated Simulation Environment) to enable utilization of the multicore processors. Using the framework provided by the OpenMP library, we aim for significant runtime reduction. One of the advantages from the implementation is inherent performance increase with the number of nonlinear components, as their computation is independent from each other. The parallelism implementation will be explained and its result discussed in this paper.