Parasitic Symmetry at a Glance: Uncovering Mixed-Signal Layout Constraints
Conference: FAC 2017 - Frontiers in Analog CAD
07/21/2017 - 07/22/2017 at Frankfurt am Main, Deutschland
Proceedings: Frontiers in Analog CAD (FAC 2017)
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Glaeser, Georg; Saft, Benjamin; Sommer, Ralf (IMMS Institut für Mikroelektronik- und Mechatronik-Systeme gGmbH, Ilmenau, Germany)
Symmetry is a fundamental concept in design of integrated circuits. Especially for layouting a given transistorlevel schematic, this concept plays a key role: Devices with matching parameters are layouted using symmetrical pattern to ensure almost equal behavior in presence of process variations. The constraints for these devices are provided by the circuit designer. Besides of the actual devices, parasitic elements such as coupling capacitors between nodes are introduced in the layout phase. These elements might issue couplings between sensitive analog nodes and digital control or switching signals degrading the circuit performance. To mitigate these effect, costly manual layout iterations are necessary. Knowledge about constraints for parasitic symmetry can significantly reduce the effort of this process. We present an efficient algorithm to determine these additional constraints automatically from a given circuit. By inserting parasitic elements into the circuit, we extract information about the susceptibility of the circuit’s nodes to parasitic influence. We combine this method with the concept of acceptance regions to identify a set of possible parasitic symmetry constraints. These candidates are validated using a systematically targeted simulation resulting in a set of constraints to be fulfilled by the layout. We demonstrate our approach by extracting 223 parasitic symmetry constraints out of a given sampling stage of a lowlight imaging system within a processing time of 6 hours.