Systematic Design of a New 3-Bit-Burst-Error Correction Code with Minimal Number of Check Bits
Conference: Zuverlässigkeit und Entwurf - 9. ITG/GMM/GI-Fachtagung
09/18/2017 - 09/20/2017 at Cottbus, Deutschland
Proceedings: ITG-Fb. 274: Zuverlässigkeit und Entwurf
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Klockmann, A.; Goessel, M. (Institute for Computer Science, University of Potsdam, Potsdam, Germany)
Georgakos, G. (Infineon Technologies AG, Neubiberg, Germany)
In this paper a new 3-bit burst-error correcting code is proposed. Compared to a 1-bit error correcting Hamming code only two additional check bits are needed and compared to a 3-bit burst-error correcting Burton code the number of check bits can be reduced by 2Since the proposed code is systematically designed by use of finite field algebra the code can be determined for an arbitrary word length and decoding is simple. Examples for different word length with up to about 1000 bits are described.The proposed code can correct single bit errors, adjacent two-bit errors, adjacent 3-bit errors and nearly adjacent 2-bit errors and may be useful for error correction in registers or register arrays, in combinational circuits and also in memories for which data-multiplexing is not used. With respect to the number of check bits the proposed code is optimal for code lenghts greater than 27.