Timing Variability Analysis of Digital CMOS Circuits

Conference: Zuverlässigkeit und Entwurf - 9. ITG/GMM/GI-Fachtagung
09/18/2017 - 09/20/2017 at Cottbus, Deutschland

Proceedings: ITG-Fb. 274: Zuverlässigkeit und Entwurf

Pages: 2Language: englishTyp: PDF

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Authors:
Rangan, Jahnavi Kasturi; Aryan, Nasim Pour; Bargfrede, Jens; Funke, Christian (Infineon Technologies A.G, Neubiberg, Germany)
Graeb, Helmut (Technische Universität München, Munich, Germany)

Abstract:
This presentation describes a framework to perform timing sensitivity evaluation of building blocks of design-dependent timing monitors due to process, voltage and temperature (PVT) variations. Design dependent timing monitors collectively monitor the timing of a chip. With the purpose of optimizing the existing design-dependent ring oscillators, analysis of sensitivity data is done and some results are demonstrated.