Physical Design Challenges and Solutions for Interposer-Based 3D Systems

Conference: Zuverlässigkeit und Entwurf - 9. ITG/GMM/GI-Fachtagung
09/18/2017 - 09/20/2017 at Cottbus, Deutschland

Proceedings: ITG-Fb. 274: Zuverlässigkeit und Entwurf

Pages: 8Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Authors:
Osmolovskyi, Sergii; Lienig, Jens (Dresden University of Technology, Dresden, Germany)

Abstract:
Three-dimensional (3D) chip integration ("More than Moore") is a promising alternative to traditional transistor scaling ("More Moore"). However, its industrial application is notably restricted by numerous design challenges, amplified by a lack of physical design tools. In order to exploit the advantages of 3D integration, layout designers and tool developers need to be fully aware of these challenges. We first investigate the variety of 3D architecture options and show that interposer-based systems are the most cost-effective candidate for heterogeneous chip design at present. Next, we review the system-level physical design challenges of interposer-based 3D ICs and outline possible solutions. Focusing on placement challenges, we propose a novel algorithm for optimal die placement on the interposer.