Investigations of Annealing Effect on TSV CMP

Conference: ICPT 2017 - International Conference on Planarization/CMP Technology
10/11/2017 - 10/13/2017 at Leuven, Belgium

Proceedings: ICPT 2017

Pages: 4Language: englishTyp: PDF

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Authors:
Rao, Can; Wang, Tongqing; Cheng, Jie; Liu, Yuhong; Lu, Xinchun (State key lab of tribology, Tsinghua University, Beijing 100084, China)

Abstract:
For Through-silicon via wafer, the quality after chemical-mechanical planarization is of great importance to 3D IC integration. The wafer profile, non-uniformity, and dishing result are the key parameters. Meanwhile, the annealing process before CMP has impact on CMP performance. In this paper we conduct TSV CMP experiments with different annealing conditions. Key parameters under consideration include annealing time and temperature. Keywords: Through-silicon Via, Chemical-mechanical Planarization, Annealing, Via dishing, Non-uniformity