A side-wall spacer process for releasing and sealing of post-CMOS MEMS pressure sensor membranes
Conference: MikroSystemTechnik 2017 - Kongress
10/23/2017 - 10/25/2017 at München, Deutschland
Proceedings: MikroSystemTechnik 2017
Pages: 4Language: englishTyp: PDF
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Authors:
Walk, Christian; Goertz, Michael (Fraunhofer Institute for Microelectronic Circuits and Systems, Duisburg, Germany)
Mokwa, Wilfried (Institute for Materials in Electrical Engineering I, RWTH Aachen University, Germany)
Vogt, Holger (Fraunhofer Institute for Microelectronic Circuits and Systems, Duisburg, Germany & University of Duisburg-Essen, Department of Electronic Components and Circuits, Germany)
Abstract:
In this work a sub-step of the fabrication of an absolute capacitive pressure sensor MEMS on top of a CMOS substrate is discussed. For low pressure applications membrane diameters of more than 100 µm are required. To apply an isotropic HF-vapour phase etching process for successful release of MEMS structures, an access to the sacrificial layer is required. Since vapour phase etching of a sacrificial layer by side openings is shown to be inappropriate due to the addressed diameters, vertically arranged openings in the structural layer of the MEMS-structure have been utilised. Different designs of possible etch accesses are simulated regarding their impact on stress. It is shown that a diameter minimisation of vertical etch-access tunnels is beneficial with respect to stress (under an applied pressure of 1500 hPa) and regarding the conditions for sealing the cavity. Therefore, a side-wall spacer process, which minimises the diameters of vertical etch-access tunnels was developed and discussed. By the use of two applied hardmasks the diameter of lithographically structured tunnels is reduced by about 260 nm (40%).