Parasitic Extraction Procedures for SiC Power Modules
Conference: CIPS 2018 - 10th International Conference on Integrated Power Electronics Systems
03/20/2018 - 03/22/2018 at Stuttgart, Deutschland
Proceedings: ETG-Fb. 156: CIPS 2018
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Kovacevic-Badstuebner, Ivana; Stark, Roger; Grossner, Ulrike (Advanced Power Semiconductor Laboratory, ETH Zurich, Zurich, Switzerland)
Guacci, Mattia; Kolar, Johann W. (Power Electronic Systems Laboratory, ETH Zurich, Zurich, Switzerland)
This paper presents an overview of the procedures performed both in academia and industry for estimating the parasitic behavior of power semiconductor packages. The modeling features and limitations of the state-of-the-art software tool, ANSYS Q3D Extractor, and the measurement methods typically used for the parasitic inductance analysis of silicon carbide (SiC) power modules are comprehensively analyzed on the example of a TO-247-3 package with a single 80 mΩ, 1.2 kV SiC power MOSFET, and of a half-bridge wire-bondless module with two 25 mΩ, 1.2 kV SiC power MOSFETs.