Design of a High Accuracy Spatially Distributed Temperature Sensor Array for CMOS Lab-on-Chip Applications
Conference: ANALOG 2018 - 16. GMM/ITG-Fachtagung
09/13/2018 - 09/14/2018 at München/Neubiberg, Deutschland
Proceedings: GMM-Fb. 91: ANALOG 2018
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Ebensberger, Yvonne C.; Lausen, Timo; Thewes, Roland (Chair of Sensor and Actuator Systems, TU Berlin, Einsteinufer 17, 10587 Berlin, Germany)
A spatially distributed temperature sensor array is suggested for Lab-on-Chip applications where precise temperature control is required. The spatially distributed kernels consist of two parasitic pnp bipolar transistors and an nMOS chopping unit. Adapting the idea of Dynamic Element Matching (DEM) and using a 10-data points per measurement approach but an averaging procedure performed in the digital domain the effect of random device parameter variations is significantly mitigated. Within the range of interest for Lab-on-Chip applications (here: 20 °C - 100 °C) and using the parameters of a commercially available foundry-based standard 180 nm CMOS process, Monte-Carlo simulations predict deviations of the measured mean values below 100 mK and 3sigma standard deviations around 200 mK, respectively, for the spatially distributed measurement kernels.