Ultra-Low-Power SAR ADC in 22 nm FD-SOI technology using Body-Biasing
Conference: ANALOG 2018 - 16. GMM/ITG-Fachtagung
09/13/2018 - 09/14/2018 at München/Neubiberg, Deutschland
Proceedings: GMM-Fb. 91: ANALOG 2018
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Jotschke, Marcel; Rao, Sunil Satish; Prautsch, Benjamin; Reich, Torsten (Fraunhofer Institute for Integrated Circuits, Division Engineering of Adaptive Systems - IIS/EAS, Dresden, Germany)
Today’s sensor applications show a rising demand on miniaturized autonomous sensors nodes with extreme requirements on power dissipation. One core functionality of these sensor nodes is the conversion of analog sensor signals to digital data for post processing and data communication. In this work a 11 bit Successive Approximation Register (SAR) ADC with minimized power dissipation is developed for a modern 22 nm FD-SOI technology. The design takes advantage of analog body biasing feature of FD-SOI technology. It achieves a power dissipation of 5 muW at a sampling rate of 100 kS/sec with an ENOB of 10 bit and 8.6 bit with and without calibration, respectively. The ADC design is flexible and easy to migrate among SOI technology nodes due to the use of generator-based Intelligent IP technology.