Design of a 28-32 GHz Low-Noise PLL with Automatic Frequency Calibration
Conference: ANALOG 2018 - 16. GMM/ITG-Fachtagung
09/13/2018 - 09/14/2018 at München/Neubiberg, Deutschland
Proceedings: GMM-Fb. 91: ANALOG 2018
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Herzel, Frank; Ergintav, Arzu; Jagdhold, Ulrich (IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany)
Kissinger, Dietmar (IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany & Technische Universität Berlin, Einsteinufer 17, 10587 Berlin, Germany)
We present the design of a low-noise Ka-band phase-locked loop (PLL) combining analog capacitive tuning with digital switching of capacitance and inductance in the resonance circuit. Based on an existing PLL circuit, we present a 30 GHz wideband PLL with 16 overlapping frequency bands controlled by four bits. The use of two parallel analog tuning loops results in a low phase noise and a robust loop bandwidth. A simple comparator circuit followed by a binary up/down counter selects the sub-band such that both analog control voltages are kept away from the rails. This guarantees a low PLL phase noise and robust operation in the presence of temperature variations and aging. The binary counter was designed in VHDL and included in the analog simulation environment for final verification.