How to Keep 4-Eyes Principle in a Design and Property Generation Flow
Conference: MBMV 2019 - 22. Workshop „Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“
04/08/2019 - 04/08/2019 at Kaiserslautern, Deutschland
Proceedings: MBMV 2019
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Devarajegowda, Keerthikumara; Kunz, Wolfgang (Infineon Technologies AG & Technische Univerität Kaiserslautern, Germany)
Ecker, Wolfgang (Infineon Technologies AG & Technische Univerität München, Germany)
A significant issue in the semi-conductor industry is ‘design productivity’, which is fast diminishing due to the constant growth in the complexity of system-on-chips and FPGAs. An important counter measure is automating development tasks such as RTL design and properties for functional verification. Frameworks that automate both design and verification tasks must satisfy 4-eyes principle as a basic requirement to ensure the quality of generated designs. In this paper, we present an generation approach developed to obey 4-eyes principle and is used to generate both RTL designs and properties for verification. The approach has been successfully used to generate RISC V processor core and several peripheral devices. The automation approach has resulted in significant reduction in the manual efforts needed and improvements in the quality of generated designs.