HBM and ASIC silicon interposer

Abstract:
The presented project shows the realization and selected analyses results of the first stage of a passive interposer chip for high performance data transfer between processor and memory dies, a 2D HBM (high bandwidth memory) interposer. The realized interposer chip can carry 8 HBM dies with each having 10’000 connections and one ASIC die with 80’000 connections. A complex design was reduced from 5 to 3 levels of redistribution layers, which significantly saves manufacturing costs. By using line/space dimensions of 4 µm a mask aligner could be utilized for exposure. Therefore big interposer dies of 44 mm by 44 mm can be produced using relatively simple lithography technology at high per wafer yield. All technology is demonstrated on 300 mm silicon wafers.