A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures

Conference: MBMV 2020 – Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen - GMM/ITG/GI-Workshop
03/19/2020 - 03/20/2020 at Stuttgart, Deutschland

Proceedings: GMM-Fb. 96: MBMV 2020

Pages: 8Language: englishTyp: PDF

Adelt, Peer; Koppelmann, Bastian; Mueller, Wolfgang; Scheytt, Christoph (Heinz Nixdorf Institut/Universität Paderborn, Paderborn, Germany)

Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.