PCB layout tool integrated loss and inductance estimation

Conference: CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems
03/24/2020 - 03/26/2020 at Berlin, Deutschland

Proceedings: ETG-Fb. 161: CIPS 2020

Pages: 5Language: englishTyp: PDF

Hoffmann, Stefan; Hoene, Eckart (Fraunhofer IZM, Berlin, Germany)
Schroeder, Bernd; Stube, Bernd; Alraai, Akram (Technical University Berlin, Germany)
Moritz, Oliver (Enasys GmbH, Berlin, Germany)
Mueller, Olaf (AE conversion, Bad Sassendorf, Germany)

This paper presents the implementation of the online inductance, loss and temperature distribution calculation integrated in a PCB layout tool. The parasitic inductances of certain current loops selected by the user are calculated with an existing PEEC solver. The developed add-on generates the 3D model automatically, activate the solver and extract the computation results. The loss solver implemented in the add-on calculates the losses and the temperature distribution according to a previously assigned current. As a result, the PCB layout designer is already efficiently supported during the design process.The method is validated using simulations and measurements of typical assemblies.