Simulating the impact of Random Telegraph Noise on integrated circuits
Conference: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
07/19/2021 - 07/22/2021 at online
Proceedings: SMACD / PRIME 2021
Pages: 4Language: englishTyp: PDF
Authors:
Saraza-Canflanca, Pablo; Camacho-Ruiz, Eros; Castro-Lopez, Rafael; Roca, Elisenda; Fernandez, Francisco V. (Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Sevilla, Spain)
Martin-Martinez, Javier; Rodriguez, Rosana; Nafria, Montserrat (Electronic Engineering Department (REDEC) group, Universitat Autònoma de Barcelona (UAB) Barcelona, Spain)
Abstract:
This paper addresses the statistical simulation of integrated circuits affected by Random Telegraph Noise (RTN). For that, the statistical distributions of the parameters of a defectcentric model for RTN are experimentally determined from a purposely designed integrated circuit with CMOS transistor arrays. Then, these distribution functions are used in a statistical simulation methodology that, taking into account transistor sizes, biasing conditions and time, can assess the impact of RTN in the performance of an integrated circuit. Simulation results of a simple circuit are shown together with experimental measurements of a circuit with the same characteristics implemented in the same CMOS technology.