Implementation of a Low Power Decimation Filter in a 180 nm HV-CMOS Technology for a Neural Recording Front-End

Abstract:
The design of decimation filters for Δ Σ Converters is a rarely discussed topic though these filters are necessary for deltasigma modulator ADCs. In this work, we present a low-power decimation filter for a neural recording front-end. We show the applied design criteria and compare different filter structures to find the most efficient implementation. The decimation filter has been implemented and simulated in a 180 nm HV-CMOS process. It achieves a low power consumption of 6.4 muW at a supply voltage of 1.2 V. The filter has a 13 bit output running at a sampling rate of 22 kHz and requires an area of 460 µm x 210 µm. The input signal’s SNDR degradation due to the filter is less than 2 dB.