Development of an over temperature detection method via internal and emulated gate resistance

Conference: CIPS 2022 - 12th International Conference on Integrated Power Electronics Systems
03/15/2022 - 03/17/2022 at Berlin, Germany

Proceedings: ETG-Fb. 165: CIPS 2022

Pages: 6Language: englishTyp: PDF

Authors:
Kawahara, Chihiro; Izuo, Shin-ichi (Advanced Technology R&D Center, Mitsubishi Electric Corporation, Amagasaki, Japan)
Brandelero, Julio; Degrenne, Nicolas (Mitsubishi Electric R&D Centre Europe, Rennes, France)

Abstract:
Over temperature detection is an important feature for protecting power modules. Classical methods include a PN junc- tion on a power die that reduces the transistor’s available area and complexifies packaging. In this study, an over temperature detection method is proposed by exploiting the temperature sensitivity of the internal gate resistance that is present on most power dies. The response to a pulsed current of an implemented gate impedance emulator circuit at a given temperature is compared to the response of the internal gate resistance (Rgin) of the Device Under Test (DUT) to the same pulsed current. Such a comparison determines whether the temperature is higher or lower than the given temperature. The emulator circuit is composed of a current mirror and an R-C circuit where R has a Rgin value at the given temperature. This implementation requires no ADCs or complex signal processing, simplifying the over temperature detection. Our first experimental measurements showed precision around 8.4oC for over temperature detection. This result indicates the potential of this method in future applications.