Coplanar Si architecture for chemiresistive hydrogen gas sensor

Conference: MikroSystemTechnik Kongress 2023 - Kongress
10/23/2023 - 10/25/2023 at Dresden, Deutschland

Proceedings: MikroSystemTechnik Kongress 2023

Pages: 5Language: englishTyp: PDF

Authors:
Singh, Karanvir (Department of Mechanical Engineering, Punjab Engineering College, Chandigarh, India)
Sharma, Ashutosh (Department of Materials Science and Engineering, Suwon, Republic of Korea)
Mager, Dario; Korvink, Jan G.; Sharma, Bharat (Institute of Microstructure Technology, Karlsruhe Institute of Technology, Eggenstein-Leopoldshafen, Germany)

Abstract:
Metal oxide semiconductor (MOX) chemiresistive sensors have garnered significant attention historically due to their cost-effectiveness and facile fabrication, making them ideal for large-scale manufacturing in sensing applications. The conventional read-out configuration relies on alterations in the resistance of the sensitive layer upon exposure to noxious and non-noxious gases. To achieve optimal outcomes in terms of sensitivity and selectivity, contemporary commercial gas sensors often operate at elevated temperatures, mandating the integration of microheating elements that exploit joule heating effects. These joule heating components can be integrated into a co-planar configuration, aligning with the active electrode pair on the same plane. Alternatively, they are commonly situated on a distinct plane beneath the electrodes, yielding a stacked topography. This paper reports a new silicon Si-wafer architecture of chemiresistive gas sensors using two electrodes simultaneously for the heating track as well as sensing with a drastic reduction in substrate area with enhanced gas sensing response, excellent selectivity towards H2 gas as compared to existing microheater-based sensor architectures. A coplanar two-terminal architecture will allow a cost-efficient design for printing chemoresistive gas sensors. This approach will promote room temperature operation with expensive metallic inks, drastic miniaturization of the Si-platform with a stacked geometry, and ease single-step printing of dielectric layers to reduce the entire device.