An Optimized FPGA Implementation of SAR Backprojection Autofocus

Abstract:
Synthetic Aperture Radar on board of small UAVs (“drones”) could enable a new field of applications. Due to their unstable flight path, autofocus processing is often required to generate usable images in this context. To enable real-time on-board processing high performance and energy-efficient hardware is required. This paper reports on an FPGA implementation of the Backprojection Autofocus algorithm using a specialized numeric optimization method called Parallel Autofocus Optimization. The hardware design is analyzed for throughput and power consumption. Results show that autofocus processing requires 36.5× the time and 24.7× the energy on our implementation, compared to Backprojection processing alone.