Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study

Abstract:
We present a comparative case study for the Chipyard framework focusing on Register Transfer Level (RTL) simulations on a High-Performance Computer (HPC) cluster equipped with FPGA accelerator cards. The RTL code was generated from a standard Rocket Chip SoC with an RV64GC-configured RISC-V Rocket core. Our FireSim evaluations investigate different software workloads with varying instruction numbers, arriving at a performance of up to 60 Million Instructions per Second (MIPS). Our Verilator experiments additionally compare different thread configurations on a HPC cluster with a desktop PC simulation host. Comparing the FireSim simulations with Verilator on a HPC cluster shows speed-ups between 4000x and 18,000x for the FireSim simulations.