Using Design Intent to Qualify and Control Lithography Manufacturing

Conference: EMLC 2006 - 22nd European Mask and Lithography Conference
01/23/2006 - 01/26/2006 at Dresden, Germany

Proceedings: EMLC 2006

Pages: 5Language: englishTyp: PDF

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Vasek, Jim; Wilkinson, Bill; Smith, Dave; Reich, Al; Garza, Cesar (Freescale Semiconductor, USA,)
Wiley, Jim; Zhao, Joyce (Brion Technologies, USA,)
Poyastro, Moshe; Troy, Brian; Nehmadi, Youval; Abraham, Zamir (Applied Materials, USA)

One of the consequences of low-k1 lithography is the discrepancy between the intended and the printed pattern, particularly in 2-D structures. Two recent technical developments offer new tools to improve manufacturing predictability, yield and control. The first enabling development provides the ability to identify the exact locations of lithography manufacturing “hot spots” using rigorous full-chip simulation. The second enabling development provides the ability to efficiently measure and characterize these critical locations on the wafer. In this paper, hot spots were identified on four critical patterned layers of a 90nm-node production process using the Brion Tachyon 1100 system. The Applied Materials OPC|Check system created the recipes necessary to automatically drive a VeritySEM CD SEM tool for hot spot measurement and analysis. Using model-predicted hot spots combined with accurate wafer metrology of critical features enabled an efficient determination of the actual process window, including process-limiting features and manufacturing lithography conditions, for qualification and control of each layer.