Statistical Interconnect Variations: Extraction and Simulation
Conference: Zuverlässigkeit und Entwurf - 1. GMM/GI/ITG-Fachtagung
03/26/2007 - 03/28/2007 at München, Germany
Proceedings: Zuverlässigkeit und Entwurf
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Kinzelbach, Harald (Infineon Technologies, 81726 Munich, Germany)
With the increasing influence of parasitic interconnect properties on the circuit performance, one also expects an increasing necessity to appropriately model the corresponding fluctuations induced by unavoidable random process variations, and to include them in subsequent circuit simulations. The paper discusses a semi-analytic approach to analyze the impact of process variations on parasitic interconnect-properties and on the resulting circuit properties. The approach allows one to extract the random interconnect manufacturing variations from a given layout. The resulting variation-extraction flow provides a parameterized variation netlist which serves as input for a Monte-Carlo approach based on analog (spice-)circuit-simulations. The approach makes it possible to analyze the impact of process-variation induced interconnect-fluctuations on the performance of realistic circuits. The final section of the paper presents first results on the impact of interconnect variations on the circuit properties of industrial circuit examples.