Towards a Systematic Design of Fault-Tolerant Asynchronous Circuits
Conference: Zuverlässigkeit und Entwurf - 1. GMM/GI/ITG-Fachtagung
03/26/2007 - 03/28/2007 at München, Germany
Proceedings: Zuverlässigkeit und Entwurf
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Schmid, Ulrich; Steininger, Andreas (Technische Universität Wien)
Veith, Helmut (Technische Universität München)
Accommodating billions of transistors on a single die, VLSI technology has reached a scale where principal physical limitations have a strong impact on design principles. Among the particular challenges are maintaining the synchronous clock abstraction in settings where wiring delays dominate over switching delays, and coping with increasing transient failure rates. In an attempt to address some of these challenges, we recently developed a clocking scheme called DARTS1. The cornerstone of this approach is a distributed fault-tolerant Tick Generation (TG) unit that implements an adaptation of a faulttolerant clock synchronization algorithm originally developed in the distributed computing context. Each functional unit on the chip is augmented with a dedicated TG unit here that generates its clock signal. Since all these TG units communicate with each other (by exchanging their clock signals), all non-faulty TG units actually supply mutually synchronized clock signals to their attached functional units.