A Performance Improvement and Error Floor Avoidance Technique for Belief Propagation Decoding of LDPC Codes
Conference: PIMRC 2005 - 16th Annual IEEE International Symposium on Personal Indoor and Mobile Radio Communications
09/11/2005 - 09/14/2005 at Berlin, Germany
Proceedings: PIMRC 2005
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Cavus, Enver (Wireless Integrated Systems Research Group, University of California, Los Angeles, CA, 90095-1594, USA)
In this work, we introduce a unique technique that improves the performance of the BP decoding in waterfall and error-floor regions by reversing the decoder failures. Based on the short cycles existing in the bipartite graph, an importance sampling simulation technique is used to identify the bit and check node combinations that are the dominant sources of error events, called trapping sets. Then, the identified trapping sets are used in the decoding process to avoid the pre-known failures and to converge to the transmitted codeword. With a minimal additional decoding complexity, the proposed technique is able to provide performance improvements for short-length LDPC codes and push or avoid error-floor behaviors of longer codes.