Chip Sized Ultra Thin Silicon Package enabling Low Cost Waferlevel Assembly and Surface Mount Technology (SMT)
Conference: Mikrosystemtechnik Kongress 2005 - Mikrosystemtechnik Kongress 2005
10/10/2005 - 10/12/2005 at Munich, Germany
Proceedings: Mikrosystemtechnik Kongress 2005
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Hase, Andreas; Hauffe, Ralf; Korth, Hillmar; Kuhmann, Jochen; Müller, Frank (Hymite GmbH, Carl-Scheele Str. 12, 12489 Berlin, Deutschland)
Heschel, Matthias; Shiv, Lior; Weichel, Steen (Hymite A/S, Diplomvej Bldg. 376, 2800 Kgs. Lyngby, Denmark)
Volume handheld-device and automotive applications demand increasing levels of integration and functionality along with lower size and cost. The challenge in the design of small MEMS and System-in-Package Sensors, RF and nano-components is to meet these goals without compromising the device performance. In this paper we present a new ultra thin wafer-level packaging technology for MEMS and the technological prerequisites. The TCE matched MEMS encapsulation is provided by hermetic metal solder sealing. SMT contacts for board level assembly are connected by vertical μ-vias to the MEMS device without the need of additional packaging like lead frame or mini DIL. We present the general concept of this high performance technology and demonstrate the features using selected examples of packaged devices.