FPGA Implementation of On-board Real-time Imaging Processor for Spaceborne SAR
Conference: EUSAR 2006 - 6th European Conference on Synthetic Aperture Radar
05/16/2006 - 05/18/2006 at Dresden, Germany
Proceedings: EUSAR 2006
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Li, Zaoshe; Yu, Weidong; Zheng, Xiaoshuang (Institute of Electronics, Chinese Academy of Sciences, China)
This paper mainly focuses on spaceborne SAR on-board real-time imaging processor, its advantages and requirements for spaceborne SAR, its FPGA based implement architecture is also presented. Based on R-D algorithm, the implemented processor composed of four modules as pre-processing module, range compressing module, corner turn memory (CTM) module and azimuth compressing module. For these four modules, we present theoretical implementations of each module, work out the simulation results and then map them to Xilinx Virtex-? FPGA platform. Furthermore, the hardware test results of CTM, range compressing module and azimuth compressing module are presented, the pre-processing module's hardware verification is on going. As a conclusion, our research shows that FPGA implementation of on-board real-time imaging processor for spaceborne SAR has many advantages, such as lower power dissipation, less volume and weight and higher reliability. Thus FPGA implementation scheme is a technology innovation for spaceborne SAR on-board real-time imaging.