An FPGA Implementation of a Memory Efficient, Low Complexity Turbo Decoder Architecture for TETRA Release 2 Application
Conference: European Wireless 2006 - 12th European Wireless Conference 2006 - Enabling Technologies for Wireless Multimedia Communications
04/02/2006 - 04/05/2006 at Athens, Greece
Proceedings: European Wireless 2006
Pages: 6Language: englishTyp: PDF
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Authors:
Nezamil, Kasra G.; Walker, Stuart D.; Fleury, Martin (University of Essex, Department of Electronic Systems Engineering, Wivenhoe Park, Colchester, Essex, C04 3SQ, U.K.)
Nezamil, Kasra G.; Stephens, Peter W. (Sepura Ltd, Radio House, St. Andrew's Rd, Cambridge, CB4 1GR, U.K.)
Abstract:
The Terrestrial Trunked Radio (TETRA) Release 2 communication standard supports different channel bandwidths and modulation techniques, and has adopted turbo code as its error coding scheme. Turbo code's inherent high complexity and long latency presents a practical problem for DSP implementation of this algorithm for TETRA Release 2 applications. In this paper, we present a low complexity, memory efficient, parallel architecture for turbo decoding on an FPGA platform, which addresses all the requirements by the standard at a low development cost, as well as low power consumption.