Overall Circuit Loss Design Method for Integrated Power Converter
Conference: CIPS 2006 - 4th International Conference on Integrated Power Systems
06/07/2006 - 06/09/2006 at Naples, Italy
Proceedings: CIPS 2006
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Takao, Kazuto; Irokawa, Hirofumi; Hayashi, Yusuke; Ohashi, Hiromichi (Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology, Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan)
Overall circuit loss design method for designing integrated power converters employing a MOSFET and a SiC-Schottky Barrier Diode (SiC-SBD) based on a minimum circuit loss estimation model has been proposed. Since the model is generalized with device parameters and circuit parameters including stray inductances and capacitances, exact converter circuit loss under real circuit conditions can be designed. In addition, a concept of a circuit loss design method, which comprises the minimum circuit loss estimation model and a device simulator, for various types of MOSFETs and SBDs is described.